 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET PCE84C886 Microcontroller for monitor OSD and auto-sync applications Preliminary specification File under Integrated Circuits, IC14 1996 Jan 08 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications CONTENTS 1 1.1 1.2 1.3 2 3 4 5 5.1 5.2 6 6.1 6.2 7 7.1 7.2 7.3 8 8.1 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 FEATURES General Special OSD GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description RESET Reset trip level Reset status ANALOG (DC) CONTROL 6 and 7-bit PWM outputs 14-bit PWM output A typical PWM output application ANALOG-TO-DIGITAL CONVERTER (ADC) Conversion algorithm ON SCREEN DISPLAY (OSD) Horizontal starting position control Vertical starting position control On-chip clock generator DISPLAY RAM ORGANIZATION Description of display RAM codes Default values of OSD after Power-on-reset Loading character data into display RAM Writing character data into display RAM CHARACTER ROM Character ROM address map Character ROM organization Combination of character font cells 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 13 13.1 13.2 13.3 14 15 16 16.1 17 18 19 20 21 22 23 23.1 23.2 23.3 24 25 26 PCE84C886 OSD CONTROL REGISTERS Derivative Register 22 Derivative Register 23 Derivative Register 33 Derivative Register 34 Derivative Register 35 Derivative Register 36 Derivative Register 37 TO FORMAT THE OSD Number of characters per row Number of rows per frame Character size selection for different display resolutions 8-BIT COUNTER (T3) I2C-BUS INTERFACE OUTPUT PORTS Mask options DERIVATIVE REGISTERS LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS DEVELOPMENT SUPPORT PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1996 Jan 08 2 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 1 1.1 FEATURES General PCE84C886 * Spacing between character rows: 0, 4, 8 and 12 scan lines * Foreground colours: 8 on a character-by-character basis * Background colours: 8 on a word-by-word basis * Background/shadowing modes: 4 modes available, No background, North shadowing, Box shadowing and Frame shadowing (raster blanking) on a frame basis * On-chip Phase-Locked Loop (PLL) oscillator (auto-sync with HSYNCN) with programmable oscillator for On Screen Display (OSD) function * Character blinking frequency: programmable using fVsync divisors of 16, 32, 64 and 128; on a frame basis * Character blinking ratios: 1 : 1, 1 : 3 and 3 : 1 * Programmable active level polarities of VSYNCN, HSYNCN, R, G, B and FB * Flexible display format by using Carriage Return Code * Auto display RAM address (DCRAR) incremented after write operation to the Character Data Register (DCRCR) * VSYNCN generates an interrupt (enabled by software) when VIEN is active. 2 GENERAL DESCRIPTION * CMOS 8-bit CPU (enhanced 8048 CPU) with 8 kbytes system ROM and 192 bytes system RAM * One 8-bit timer/event counter (T1) and one 8-bit counter triggered by external input (T3) * Four single level vectored interrupt sources: external (INTN), counter/timer, I2C-bus and VSYNCN * 2 directly testable inputs T0 and T1 * On-chip oscillator clock frequency: 1 to 10 MHz * On-chip Power-on-reset with low power detector * Twelve quasi-bidirectional I/O lines, configuration of each I/O line individually selected by mask option * Idle and Stop modes for reduced power consumption * Operating temperature: -25 to +85 C * Operating voltage: 4.5 to 5.5 V * Package: SDIP42. 1.2 Special * Master-slave I2C-bus interface * Four 6-bit Pulse Width Modulated outputs (PWM4 to PWM7) * Four 7-bit Pulse Width Modulated outputs (PWM0 to PWM3) * One 14-bit Pulse Width Modulated output (PWM8) * Three 4-bit ADC channels * 16 derivative I/O ports. 1.3 OSD * Maximum dot frequency (fOSD): 14 MHz * Display RAM: 64 x 10 bits * Display character fonts: 62 + 2 special reserved codes * Character matrix: 12 x 18 (no spacing between characters) * 4 character sizes: 1H/1V, 1H/2V, 1H/3V and 1H/4V * 64 Horizontal starting positions (4 dots for each step) * 64 Vertical starting positions (4 scan lines for each step) 3 ORDERING INFORMATION The PCE84C886 is a member of the 84CXXX CMOS microcontroller family. It is suitable for use in 14", 15" and 17" auto-sync monitors for OSD and auto-sync applications. The device uses the PCE84CXX processor core and has 8 kbytes of ROM and 192 bytes of RAM. I/O requirements are adequately catered for with 12 general purpose bidirectional I/O lines plus 16 function combined I/O lines. 9 PWM analog outputs are provided specifically for analog control purposes and also three 4-bit ADCs. The device has an 8-bit counter, suitable for use in pulse counting applications; an 8-bit timer/counter with programmable clock and an on-chip programmable PLL oscillator that generates the OSD clock. In addition to all these features a master-slave I2C-bus interface, 2 directly testable lines and an enhanced OSD facility for flexible screen format (64 character types) are also provided. The block diagram of the PCE84C886 is shown in Fig.1. PACKAGE TYPE NUMBER NAME PCE84C886 1996 Jan 08 SDIP42 DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) 3 VERSION SOT270-1 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 4 BLOCK DIAGRAM PCE84C886 handbook, full pagewidth VOW0 T1 INTN / T0 T3 FB VOW2 C VSYNCN HSYNCN VOW1 (3) (3) VDD XTAL1 (IN) 8-BIT TIMER / EVENT COUNTER 8-BIT COUNTER ROM 8 kbytes RAM 192 bytes CPU ON SCREEN DISPLAY XTAL2 (OUT) 8-bit internal bus RESET PARALLEL I/O PORTS PCF84CXX core excluding ROM / RAM 8-BIT I/O PORTS 2 TEST / EMU 4 x 6-BIT PWM 4 x 7-BIT PWM 14-BIT PWM 3 x 4-BIT ADC I C-BUS INTERFACE V SS 8 4 8 4 4 MLC067 (1) PWM0 to PWM7 (2) PWM8 (2) ADC0 to ADC2 (3) SDA (3) SCL P0 P1 DP0 DP1 DP2 (1) Alternative function of DP0. (2) Alternative function of DP1. (3) Alternative function of DP2. Fig.1 Block diagram. 1996 Jan 08 4 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 5 5.1 PINNING INFORMATION Pinning PCE84C886 handbook, halfpage FB VOW2 VOW1/DP22 VOW0/DP23 VSYNCN HSYNCN P10 P11 DP13/PWM8 P12 T3 P14 P00 P01 P02 P03 P04 P05 P06 P07 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 MLC068 42 VDD 41 40 39 38 37 36 35 34 33 PCE84C886 32 31 30 29 28 27 26 25 24 23 22 C DP20/SDA DP21/SCL DP10/ADC0 DP11/ADC1 DP12/ADC2 INTN/T0 T1 RESET XTAL2 (OUT) XTAL1 (IN) TEST/EMU DP00/PWM0 DP01/PWM1 DP02/PWM2 DP03/PWM3 DP04/PWM4 DP05/PWM5 DP06/PWM6 DP07/PWM7 Fig.2 Pin configuration. 1996 Jan 08 5 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 5.2 Pin description SDIP42 package SYMBOL FB VOW2 VOW1/DP22 VOW0/DP23 VSYNCN HSYNCN P10 P11 DP13/PWM8 P12 T3 P14 P00 to P07 VSS DP00/PWM0 to DP07/PWM7 TEST/EMU XTAL1 (IN) XTAL2 (OUT) RESET T1 INTN/T0 DP10/ADC0 DP11/ADC1 DP12/ADC2 DP21/SCL DP20/SDA C VDD PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 to 20 21 29, 28, 27, 26 25, 24, 23, 22 30 31 32 33 34 35 38 37 36 39 40 41 42 DESCRIPTION Video Fast Blanking output. Video character output VOW2. PCE84C886 Table 1 Video character output VOW1 or Derivative Port line DP22. Video character output VOW0 or Derivative Port line DP23. Vertical synchronization signal input. Horizontal synchronization signal input. Port line 10 or emulation input DXWR. Port line 11 or emulation input DXRD. Derivative I/O port or PWM8 output. Port line 12 or emulation input DXALE. Secondary 8-bit counter input (Schmitt trigger). Port line 14 or emulation output DXINT. General I/O port lines. Ground. Derivative I/O ports or PWM outputs. Control input for testing and emulation mode, normally LOW. Oscillator input pin for system clock. Oscillator output pin for system clock. Reset input; active LOW input initializes device. Direct testable pin or event counter input. External interrupt or direct testable pin. Derivative I/O port or ADC Channel 0 input. Derivative I/O port or ADC Channel 1 input. Derivative I/O port or ADC Channel 2 input. Derivative port line or I2C-bus clock input. Derivative port line or I2C-bus data input. External capacitor input for on-chip oscillator. Power supply. 1996 Jan 08 6 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 6 RESET PCE84C886 The RESET pin may be used as an active LOW input to initialize the microcontroller to a defined state. An active reset can be generated by driving the RESET pin from an external logic device. Such an active reset pulse should not fall off before VDD has reached its fxtal-dependent minimum operating voltage. A Power-on-reset can be generated using an external RC circuit. To avoid overload of the internal diode, an external diode should be added in parallel if CRESET 2.2 F. The RC circuit is shown in Fig.3. 6.1 Reset trip level Fig.3 External components for RESET pin. handbook, halfpage V DD R RESET ( 100 k) RESET C RESET V SS internal reset PCA84C8XX MLC259 The RESET trip voltage level is masked to 1.3 V in the PCE84C886. If any input (for example Hsync) goes HIGH before VDD is applied, latch-up may occur and in this situation the PCE84C886 cannot be reset. The cause and effect of latch-up is shown in Fig.4. 6.2 Reset status handbook, halfpage V DD V DD internal V DD * Derivative Registers reset status; see Table 38 for details * Program Counter 00H * Memory Bank 0 * Register Bank 0 * Stack Pointer 00H * All interrupts disabled * Timer/event counter 1 stopped and cleared * Timer pre-scaler modulo-32 (PS = 0) * Timer flag cleared * Serial I/O interface disabled (ESO = 0) and in slave receiver mode * Idle and Stop mode cleared. R RESET RESET C RESET V SS Hsync HSYNCN V SS PCE84C886 internal reset MLC260 Fig.4 The influence of an active HIGH signal being applied before Power-on-reset. 1996 Jan 08 7 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 7 ANALOG (DC) CONTROL PCE84C886 The duty cycle of outputs PWM0 to PWM7 is dependent on the programmable contents of the data latches (Registers 10 to 17 respectively). As the clock frequency of each PWM circuit is 13 x fxtal, the pulse width of the pulse generated can be calculated as shown below. 3 x ( PWMn ) Pulse width = --------------------------------f xtal Where (PWMn) is the decimal value held in the data latch. The maximum repetition frequency (fPWM) of the 6 and 7-bit PWM outputs is shown below. f xtal For the 6-bit PWM outputs: f PWM = --------192 f xtal For the 7-bit PWM outputs: f PWM = --------384 The block diagram for the 6 and 7-bit PWM outputs is shown in Fig.5. The PCE84C886 has nine Pulse Width Modulated (PWM) outputs for analog control purposes e.g. brightness, contrast, H-shift, V-shift, H-width, V-size, E-W, R (or G or B) gain control etc. Each PWM output generates a pulse pattern with a programmable duty cycle. The nine PWM outputs are specified below: * 4 PWM outputs with 6-bit resolution (PWM4 to PWM7) * 4 PWM outputs with 7-bit resolution (PWM0 to PWM3) * 1 PWM output with 14-bit resolution (PWM8). The 6 and 7-bit PWM outputs are described in Section 7.1; the 14-bit PWM output is described in Section 7.2 and a typical PWM output application is described in Section 7.3. 7.1 6 and 7-bit PWM outputs PWM outputs PWM0 to PWM7 share the same pins as Derivative Port lines DP00 to DP07 respectively. Selection of the pin function as either a PWM output or a Derivative Port line is achieved using the appropriate PWMnE bit in Register 21 (see Table 38). The polarity of the PWM outputs is programmable and is selected by the P7LVL and P6LVL bits in Register 23 (see Section 12.2). internal data bus handbook, full pagewidth f xtal 3 6 or 7-BIT PWM DATA LATCH P6LVL/P7LVL DP0x data I/O PWMnE 6 or 7-BIT DAC PWM CONTROLLER Q Q MLC069 DP0x/PWMx Fig.5 Block diagram for 6 and 7-bit PWMs. 1996 Jan 08 8 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 f xtal handbook, full pagewidth 3 64 or 128 00 1 2 3 m m+1 m+2 64 or 128 1 01 m 63 or 127 MLC261 decimal value PWM data latch Fig.6 Typical non-inverted output pulse patterns for 6 or 7-bit PWM outputs. 1996 Jan 08 9 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 7.2 14-bit PWM output 7.2.1 COARSE ADJUSTMENT PCE84C886 PWM8 shares the same pin as Derivative Port line DP13. Selection of the pin function as either a PWM output or as a Derivative Port line is achieved using the PWM8E bit in Register 22 (see Section 12.1). The Block diagram for the 14-bit PWM output is shown in Fig.7 and comprises: * Two 7-bit latches: PWM8L (Register 18) and PWM8H (Register 19) * 14-bit data latch (PWMREG) * 14-bit counter * Coarse pulse controller * Fine pulse controller * Mixer. Data is loaded into the 14-bit data latch (PWMREG) from the two 7-bit data latches (PWM8H and PWM8L) when either of these data latches is written to. The upper seven bits of PWMREG are used by the coarse pulse controller and determine the coarse pulse width; the lower seven bits are used by the fine pulse controller and determine in which subperiods fine pulses will be added. The outputs OUT1 and OUT2 of the coarse and fine pulse controllers are `ORED' in the mixer to give the PWM8 output. The polarity of the PWM8 output is programmable and is selected by the P8LVL bit in Register 23, this is described in Section 12.2. As the 14-bit counter is clocked by fxtal/3, the repetition times of the coarse and fine pulse controllers may be calculated as shown below. 384 Coarse controller repetition time: t sub = --------f xtal 49152 Fine controller repetition time: t r = --------------f xtal Figure 8 shows typical PWM8 outputs, with coarse adjustment only, for different values held in PWM8H. Figure 9 shows typical PWM8 outputs, with coarse and fine adjustment, after the coarse and fine pulse controller outputs have been `ORED' by the mixer. An active HIGH pulse is generated in every subperiod; the pulse width being determined by the contents of PWM8H. The coarse output (OUT1) is LOW at the start of each subperiod and will remain LOW until the time [ 3 f xtal x ( PWM8H + 1 ) ] has elapsed. The output will then go HIGH and remain HIGH until the start of the next subperiod. The coarse pulse width may be calculated as shown below. 3 Pulse duration = ( 127 - PWM8H ) x -------f xtal 7.2.2 FINE ADJUSTMENT Fine adjustment is achieved by generating an additional pulse in specific subperiods. The pulse is added at the start of the selected subperiod and has a pulse width of 3/fxtal. The contents of PWM8L determine in which subperiods a fine pulse will be added. It is the logic 0 state of the value held in PWM8L that actually selects the subperiods. When more than one bit is a logic 0 then the subperiods selected will be a combination of those subperiods specified in Table 2. For example, if PWM8L = 111 1010 then this is a combination of: * PWM8L = 111 1110: subperiod 64 and * PWM8L = 111 1011: subperiods 16, 48, 80 and 112. Pulses will be added in subperiods 16, 48, 64, 80 and 112. This example is illustrated in Fig.10. When PWM8L holds 111 1111 fine adjustment is inhibited and the PWM8 output is determined only by the contents of PWM8H. Table 2 Additional pulse distribution ADDITIONAL PULSE IN SUBPERIOD 64 32 and 96 16, 48, 80 and 112 8, 24, 40, 56, 72, 88, 104 and 120 4, 12, 20, 28, 36, 44, 52...116 and 124 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127 PWM8L 111 1110 111 1101 111 1011 111 0111 110 1111 101 1111 011 1111 1996 Jan 08 10 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth Internal data bus `MOVE instruction' PWM8H PWM8L `MOV instruction' 7 7 DATA LOAD TIMING PULSE LOAD PWMREG 7 COARSE 7-BIT PWM OUT1 7 FINE PULSE GENERATOR OUT2 polarity control bit MIXER Q Q PWM8 output P8LVL Q14 to 8 14-BIT COUNTER MLC071 Q7 to 1 f tdac = f xtal 3 Fig.7 14-bit PWM Block diagram. 1996 Jan 08 11 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, f xtal full pagewidth 3 127 0 1 2 m m+1 m+2 127 0 1 00 01 m 127 MLC263 decimal value PWM8H data latch Fig.8 Non-inverted PWM8 output patterns - Coarse adjustment only. f full handbook, xtalpagewidth 3 127 0 1 2 m m+1 m+2 127 0 1 00 01 m 127 MLC262 decimal value PWM8H data latch Fig.9 Non-inverted PWM8 output patterns - Coarse and Fine adjustment. 1996 Jan 08 12 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 tr handbook, full pagewidth t sub0 t sub16 t sub32 t sub48 t sub64 t sub80 t sub96 t sub112 t sub127 111 1110 111 1011 111 1010 MLC755 PWM8L Fig.10 Fine adjustment output (OUT2). 7.3 A typical PWM output application A typical PWM application is shown in Fig.11. The buffer is used to reduce jitter on the OSD. R1 and C1 form the integration network the time constant of which should be equal to or greater than 5 times the repetition period of the PWM output pattern. In order to smooth a changing PWM output a high value of C1 should be chosen. The value of C1 will normally be in the range 1 to 10 F. The potential divider chain formed by R2 and R3 is used only when the output voltage is to be offset. The output voltages for this application are calculated using Equations (1) and (2). R3 x supply voltage V max = ---------------------------------------------------(1) R1 x R2 R3 + --------------------R1 + R2 R1 x R3 --------------------- x supply voltage R1 + R3 = -----------------------------------------------------------------R1 x R3 R2 + --------------------R1 + R3 handbook, halfpage supply voltage R2 R1 PWMn analog output C1 R3 PCE84C886 VSS MLC070 V min (2) The loop from the PWM pin through R1 and C1 to VSS will radiate high frequency energy pulses. In order to limit the effect of this unwanted radiation source, the loop should be kept short and a high value of R1 selected. The value of R1 will normally be in the range 3.3 to 100 k. It is good practice to avoid sharing VSS (pin 21) with the return leads of other sensitive signals. Fig.11 Typical PWM output circuit. 1996 Jan 08 13 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 8 ANALOG-TO-DIGITAL CONVERTER (ADC) PCE84C886 The channel selector, consisting of three analog switches, is controlled by bits ADCS1 and ADCS0 in Register 20 as highlighted in Table 4. Table 4 Selection of ADC channel ADCS0 0 1 0 1 CHANNEL SELECTED ADC0 ADC1 ADC2 reserved The 3 channel ADC comprises a 4-bit Digital-to-Analog Converter (DAC); a comparator; an analog channel selector and control circuitry. As the digital input to the 4-bit DAC is loaded by software (a subroutine in the program), it is known as a software ADC. The block diagram is shown in Fig.12. The ADC inputs ADC0 to ADC2 share the same pins as Derivative Port lines DP10 to DP12 respectively. Selection of the pin function as either an ADC input or as a Derivative Port line is achieved using bits ADCE0 to ADCE2 in Register 22. When ADCEn = 1, the ADC function is enabled (see Section 12.1). The 4-bit DAC analog output voltage (Vref) is determined by the decimal value of the data held in bits DAC0 to DAC3 of Register 20. Vref is calculated as shown in Equation (3) and Table 3 lists the Vref values assuming VDD = 5 V. V DD (3) V ref = --------- x ( DAC value + 1 ) 16 When the analog input voltage is higher than Vref, the COMP bit in Register 20 will be HIGH. Table 3 DAC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Selection of Vref DAC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DAC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DAC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vref (V) 0.3125 0.6250 0.9375 1.2500 1.5625 1.8750 2.1875 2.5000 2.8125 3.1250 3.4375 3.7500 4.0625 4.3750 4.6875 5.0000 ADCS1 0 0 1 1 8.1 Conversion algorithm There are many algorithms available to achieve the ADC conversion. The algorithm described below and shown in Fig.13 uses an iteration process. 1. Select ADCn channel for conversion. Channel selection is achieved using bits ADCS1 and ADCS0 in Register 20. 2. Set the digital input to the DAC to 1000. The digital input to the DAC is selected using bits DAC3 to DAC0 in Register 20. 3. Determine the result of the compare operation. This is achieved by reading the COMP bit in Register 20 using the instruction MOV A, D20. If COMP = 1; the analog input voltage is higher than the reference voltage (Vref). If COMP = 0; the analog input voltage is lower than the reference voltage (Vref). 4. If COMP = 1; then the analog input voltage is higher than the reference voltage (Vref) and therefore the digital input to the DAC needs to be increased. Set the input to the DAC to 1100. 5. If COMP = 0; then the analog input voltage is lower than the reference voltage (Vref) and therefore the digital input to the DAC needs to be decreased. Set the input to the DAC to 0100. 6. Determine the result of the compare operation by reading the COMP bit in Register 20. 1996 Jan 08 14 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 7. For the DAC = 1100 case If COMP = 1; then the analog input voltage is still greater than Vref and therefore the digital input to the DAC needs to be increased again. Set the input to the DAC to 1110. If COMP = 0; then the analog input voltage is now less than Vref and therefore the digital input to the DAC needs to be decreased. Set the input to the DAC to 1010 8. For the DAC = 0100 case If COMP = 1; then the analog input voltage is now greater than Vref and therefore the digital input to the DAC needs to be increased. Set the input to the DAC to 0110. If COMP = 0; then the analog input voltage is still lower than Vref and therefore the digital input to the DAC needs to be decreased again. Set the input to the DAC to 0010. PCE84C886 9. The operations detailed in 6, 7 and 8 above are repeated and each time the digital input to the DAC is changed accordingly; as dictated by the state of the COMP bit. The complete process is shown in Fig.13. Each time the DAC input is changed the number of values which the analog input can take is reduced by half. In this manner the actual analog value is honed into. The value of the analog input (VA) is determined using Equation (4): V DD V A = --------- x ( DAC value + 1 ) 16 (4) As the conversion time of each compare operation is greater than 6 s but less than 9 s; a NOP instruction is recommended to be used in between the instructions that change the value of Vref; select the ADC channel and read the COMP bit. handbook, full pagewidth DERIVATIVE PORT SELECTOR EN0 EN1 EN2 Internal bus DP10/ADC0 DP11/ADC1 DP12/ADC2 ADC CHANNEL SELECTOR + Vref COMPARATOR - EN COMP bit `MOV A, D20' instruction to read COMP bit Channel selection ADCS1 ADCS0 ENABLE SELECTOR 4-BIT DAC ADCE0 ADCE1 ADCE2 DAC3 DAC2 DAC1 DAC0 MLC072 ADC enable selection DAC value selection Fig.12 Block diagram of 3 channel ADC. 1996 Jan 08 15 Fig.13 Example of converting algorithm for software ADC. handbook, full pagewidth 1996 Jan 08 Value = 1000 T COMP = 1 F Value = 1100 Value = 0100 T COMP = 1 F T COMP = 1 F Value = 1110 Value = 1010 Value =0110 Value = 0010 Philips Semiconductors Microcontroller for monitor OSD and auto-sync applications 16 T COMP = 1 T 1111 COMP = 1 F T COMP = 1 F T COMP = 1 F T COMP = 1 F Value = 1111 Value = 1101 Value = 1011 Value = 1001 Value = 0111 Value = 0101 Value = 0011 Value = 0001 COMP = 1 F 1110 T 1101 F 1100 T 1011 COMP = 1 F 1010 T 1001 COMP = 1 F 1000 T 0111 COMP = 1 F 0110 T 0101 COMP = 1 F 0100 T 0011 COMP = 1 F 0010 T 0001 COMP = 1 F 0000 MLC073 Preliminary specification PCE84C886 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 9 ON SCREEN DISPLAY (OSD) 9.3 On-chip clock generator PCE84C886 The OSD feature of the PCE84C886 enables the user to display information on the monitor screen. Display information can be created using 62 customer designed characters, a space character and a carriage return code. The OSD block diagram is shown in Fig.14. 9.1 Horizontal starting position control The on-chip oscillator generates an OSD clock that is auto-sync with Hsync. The frequency of the OSD clock is programmable and is determined by the contents of Register 25 which forms the 7-bit counter. The OSD clock frequency is calculated as follows: f OSD = f Hsync x 2 x ( Register 25 ) Where (Register 25) denotes the decimal value held in Register 25. The block diagram of the OSD clock is shown in Fig.16. The internal reference frequency is connected to Hsync, and if the frequency of Hsync changes, the output frequency (fOSD) will be changed linearly. Therefore, the character width is not effected by changes in the frequency of Hsync. The internal Hsync signal is designed active HIGH, consequently fPLL is synchronized with the falling edge of this signal. The OSD clock is enabled/disabled by the state of the EN bit in Register 34; see Section 12.4. When the OSD clock is disabled the oscillator remains active, therefore the transient time from the OSD clock start-up to locking into the external Hsync signal is reduced. As the on-chip oscillator is always active after power-on, when the OSD clock is enabled no large currents flow (as in the case of RC or LC oscillators) and therefore radiated noise is dramatically reduced. The horizontal starting position counter is incremented every OSD clock after Hsync becomes inactive and is reset when Hsync becomes active. The horizontal starting position of the display row is determined by the contents of Register 36; 1 of 64 positions may be selected as explained in Section 12.6. The polarity of the active state of the HSYNCN input is programmable and is determined by the Hp bit in Register 34; see Section 12.4. The active HIGH and active LOW states as selected by the Hp bit are shown in Fig.15. 9.2 Vertical starting position control The vertical starting position counter is incremented every Hsync cycle and is reset when Vsync becomes active. The vertical starting position of the display row is determined by the contents of Register 35; 1 of 64 positions may be selected as explained in Section 12.5. The vertical starting position of the display is dependent upon the number of scan lines per frame. To achieve the same starting position with different display resolutions, only the contents of Register 35 need to be changed, the contents of Register 36 remain the same. The lowest vertical starting position that can be selected, is located on the 256th scan-line. However, lower positions may be achieved using the Carriage Return Code. When the selected horizontal and vertical starting positions are reached on screen; the OSD is enabled. The character selected in display RAM is then displayed. The polarity of the active state of the VSYNCN input is programmable and is determined by the Vp bit in Register 34; see Section 12.4. The active HIGH and active LOW states as selected by the Vp bit are shown in Fig.15. 1996 Jan 08 17 Fig.14 OSD block diagram. handbook, full pagewidth 1996 Jan 08 CPU bus CHARACTER SIZE CONTROL COUNTER WRITE ADDRESS ADDRESS BUFFER SELECTOR DISPLAY CHARACTER RAM CONTROL REGISTER R1 C R2 C1 HORIZONTAL POSITION REGISTER/ COUNTER PLL OSCILLATOR INSTRUCTION DECODER CONTROL REGISTER VERTICAL POSITION REGISTER/ COUNTER control signals DISPLAY ROM Philips Semiconductors Microcontroller for monitor OSD and auto-sync applications 18 HSYNCN VSYNCN DISPLAY CONTROL AND OUTPUT STAGE R G B FB MLC285 POLARITY CONTROL INTERNAL SYNCHRONOUS CIRCUIT VOW1 VOW0 VOW2 FB Preliminary specification PCE84C886 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth HSYNCN/VSYNCN pin Hp/Vp = 0 (active LOW) character display interval HSYNCN/VSYNCN pin Hp/Vp = 1 (active HIGH) MLC286 Fig.15 HSYNCN and VSYNCN active level selection. handbook, full pagewidth C PHASE/ FREQUENCY DETECTOR CHARGE PUMP AND LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR HSYNCN (30 to 64 kHz) divided by N PROGRAMMABLE 7-BIT COUNTER 2 f PLL f OSD MLC074 OSD disable Fig.16 Block diagram for OSD oscillator. 1996 Jan 08 19 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 10 DISPLAY RAM ORGANIZATION The display RAM is organized as 64 x 10 bits. The general format of each RAM location is as follows. Bits <9-4> hold character data (62 customer designed character fonts plus two reserved codes). Bits <3-0> contain the attributes of the character font, for example colour, character size, blinking etc. 10.1 Description of display RAM codes PCE84C886 There are three data formats for display RAM code: 1. Character Font Code 2. Carriage Return Code 3. Space Code. The three data formats are shown in Tables 5, 6 and 7. Table 5 9 C5 Format of Character Font Code 8 C4 7 C3 6 C2 5 C1 4 C0 3 T3 2 T2 Foreground colour 1 T1 0 T0 Blink Character Font Code (00H - 3DH) Table 6 9 C5 Format of Carriage Return Code 8 C4 7 C3 6 C2 5 C1 4 C0 3 T3 2 T2 1 T1 0 T0 Carriage Return Code (3EH) Table 7 9 C5 Format of Space Code 8 C4 7 C3 6 C2 5 C1 4 C0 Character size Line Spacing 3 T3 2 T2 Background colour 1 T1 0 T0 End Space Code (3FH) 1996 Jan 08 20 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 10.1.1 CHARACTER FONT CODE PCE84C886 Table 10 Selection of character size T3 0 0 1 1 Note T2 0 1 0 1 CHARACTER DOT SIZE(1) 1H/1V 1H/2V 1H/3V 1H/4V If bits <9-4> are in the range (00H to 3DH), then this is a Character Font Code and 1 from 62 customer designed character fonts can be selected. Bits <3-1> determine the colour of the character, a choice of 8 colours being available. Bit <0> determines whether the character blinks or not. The format of the Character Font Code is shown in Table 5. Table 8 Selection of Foreground colour T2 (GREEN) 0 0 1 1 0 0 1 1 T1 (BLUE) 0 1 0 1 0 1 0 1 COLOUR T3 (RED) 0 0 0 0 1 1 1 1 Table 9 1. H is the OSD clock period; V is the number of horizontal scan lines per dot. Table 11 Selection of line spacing black blue green cyan red magenta yellow white T1 0 0 1 1 10.1.3 T0 0 1 0 1 SPACE CODE LINE SPACING 0H line 4H line 8H line 12H line Selection of Blinking function T0 0 1 BLINKING OFF ON 10.1.2 CARRIAGE RETURN CODE If bits <9-4> hold 3EH, then this is the Carriage Return Code. The current display line is terminated (a transparent pattern appears on the screen) and the next character will be displayed at the beginning of the next line. Bits <3-2> select the size of the of the character to be displayed on the next line. Bits <1-0> determine the spacing between lines of displayed characters. Spacing is a multiple of the number of horizontal scan lines. In order to prevent vertical jumping of the display, the first line should be a non-displayed line i.e. the Carriage Return Code. The line spacing for this code must not be zero (see Table 11). The format of the Carriage Return Code is shown in Table 6. If bits <9-4> hold 3FH, then this is the Space Code. A transparent pattern, equal to one character width, will be displayed on the screen. Bits <3-1> determine the background colour of the characters including the Space Code in Box shadowing mode but following the Space Code in North shadowing mode. See Sections 12.4 and 12.3.1 for more details. Background colour selection is the same as foreground colour selection. Bit <0> is the End-of-Display bit and indicates the end of display of the current screen before exhaustion of display RAM (i.e. before the 64th RAM location). The format of the Space Code is shown in Table 7. Table 12 End of display control T0 0 1 DISPLAY CONTROL continue display of next character; this is also the default setting end of display 1996 Jan 08 21 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 10.2 Default values of OSD after Power-on-reset 10.3.2 PCE84C886 DCR ATTRIBUTE REGISTER (DCRTR) * Frequency of OSD clock: undefined, must be programmed * Background/Shadowing mode: No background mode * Background/Shadowing colour: blue * Character size: 1H/1V * OSD disabled * Full 64 display RAM displayed (End-of-Display bit = 0) * VOW1E and VOW0E disabled * Horizontal starting position: 5th dot * Vertical starting position: 256th scan-line * Polarity of HSYNCN: active LOW * Polarity of VSYNCN: active LOW * Output polarities of FB, VOW0 to VOW2: active HIGH * Blinking ratio: 3 : 1 * Blinking frequency: 1 128 This is Derivative Register 31 and holds the character font attribute data. The data will be loaded into bits <3-0> of the location in RAM pointed to by the contents of DCRAR. Bits 7 to 4 are reserved. Table 14 DCR Attribute Register (DCRTR) 7 - 10.3.3 6 - 5 - 4 - 3 T3 2 T2 1 T1 0 T0 DCR CHARACTER REGISTER (DCRCR) This is Derivative Register 32 and holds the character data that will be loaded into bits <9-4> of the location in RAM addressed by the contents of DCRAR. Bits 7 and 6 are reserved. Table 15 DCR Character Register (DCRCR) x fVsync * Frame background colour: blue. After a Power-on-reset, the OSD can be set-up as required by selecting the Space Code as the first character (address 0) and the Carriage Return Code as the next character (address 1). This procedure allows the user to select the initial background colour; character size and inter-line spacing. 10.3 Loading character data into display RAM 7 - 10.4 6 - 5 C5 4 C4 3 C3 2 C2 1 C1 0 C0 Writing character data into display RAM The procedure for writing character data into the display RAM is as follows: 1. Select the start address in display RAM. The start address is stored in DCRAR and can take any value between 0 and 63. 2. Load the character attributes into DCRTR. If the attributes of a series of displayed characters are the same, only DCRCR needs to be updated. 3. Load the character data into DCRCR. The character data will specify either a Character Font Code, the Carriage Return Code or the Space Code. This operation loads the selected RAM location with the data held in registers DCRTR and DCRCR. The address held in DCRAR is then incremented by `1' pointing to the next RAM location in anticipation of the next operation. After a master reset the contents of DCRAR, DCRTR and DCRCR are zero. Three Derivative Registers are used to address and load data into the display RAM. These registers are described below. 10.3.1 DCR ADDRESS REGISTER (DCRAR) This is Derivative Register 30 and holds the address of the location in display RAM to which the data held in registers DCRTR and DCRCR will be written to. 1 of 64 locations can be addressed. Bits 7 and 6 are reserved. The contents of this register are automatically incremented after each write operation to a RAM address, and become zero on overflow. Table 13 DCR Address Register (DCRAR) 7 - 6 - 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0 1996 Jan 08 22 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 11 CHARACTER ROM 64 character fonts may be held in ROM; 62 customer selected character fonts plus the Carriage Return Code and the Space Code. Customer selected fonts are mask programmable. Each character font is stored in a 12 x 19 dot matrix. However, only elements in Rows 1 to 18 can be selected as visible dots on the screen. Row 0 is only used for the combination of two characters in a vertical direction when North shadowing mode is selected. 11.1 Character ROM address map PCE84C886 The combination of two cells in a horizontal direction is straight forward and requires no special precautions to be taken. When combining character cells in this manner all 4 Background/Shadowing modes are available. An example of combining two character font cells in a horizontal direction is shown in Fig.19. However, the combination of two character font cells in a vertical direction is more difficult and care must be taken; otherwise, the new pattern may be created with gaps in its shadowing. An example of a character pattern with gaps is shown in Fig.20. Providing the steps listed below are followed no problems with shadowing will occur. * The line spacing between two rows of characters must be programmed to 0H. This procedure is explained in Section 10.1.2. * If the North shadowing mode is selected then when combining two character cells in a vertical direction Row 0 must contain the same bit pattern as held in Row 18 of the character directly above it. This is shown in Fig.21. * If North shadowing is not required then Row 0 should contain all zeros. Figure 17 shows the ROM address map. Addresses 3EH and 3FH hold the reserved codes for carriage return and space functions, respectively. Addresses (00H to 3DH) hold the customer selected character font codes. 11.2 Character ROM organization ROM is divided into two parts: ROM1 and ROM2. The organization of the bit patterns stored in ROM 1 and ROM 2 and the file format to submit to Philips for customized character sets is shown in Fig.18. Regarding Fig.18 the following points should be noted. 1. Row 0 of each font is reserved for vertical combination of two fonts. 2. Binary 1 denotes visual dots. 3. ROM1 and ROM2 data files are in INTEL hex format on a byte basis. Each byte is structured high nibble followed by low nibble. 4. The unused last byte of each font in ROM1 must be filled with FFH. 5. The unused last 212 bytes in ROM2 must be filled with the same data as held in the corresponding address in ROM1. 6. The data bytes of the last 2 reserved fonts (Carriage Return and Space Codes) should be filled with 00H. 7. CS denotes Checksum. A software package (OSDGEM) that assists in the design of character fonts on-screen and that also automatically generates the bit pattern HEX files is available on request. The package is run under the MS-DOS environment for IBM compatible PCs. 11.3 Combination of character font cells 0 Mask Programmable Font reserved code Two (or more) character font cells may be combined in a horizontal or vertical direction to create a new higher resolution pattern. 61 (3DH) 62 (3EH) 63 (3FH) Carriage return code Space code MLC287 Fig.17 ROM address map. 1996 Jan 08 23 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 MSB handbook, full pagewidth Column LSB 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 3 2 2 3 2 2 3 2 2 3 0 0 5 5 0 0 0 0 00 FC 20 20 FC 20 20 FC 20 20 FF 01 01 53 52 06 0C 58 30 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM1 000 ROM2 3FC 220 220 3FC 220 220 3FC 220 220 3FF 001 001 553 552 006 00C 058 030 Row ROM1 :10000000 :10001000 :10002000 byte # 0 1 __ __ __ 5 6__ 7 __8 __9 __ __ __ __ __ A B C DE __ __ 2 3 4 __ 00 00 22 FC 03 22 20 F2 3F 01 20 55 0C 00 03 < - - - - - - - - - DATA FOR FONT 2 - - - - - - - - - - 12 34 - - - > < - - - - - - - - - DATA FOR FONT 3 - - - - - - - - - - 56 78 - - - > F FF CS FF CS FF CS ROM2 : 1 0 0 0 0 0 0 0 FC 03 22 20 C2 3F 20 12 00 53 65 00 58 00 03 FF C S FF C S FF C S MLC076 : 1 0 0 0 1 0 0 0 < - - - - - - - - - DATA FOR FONT 2 - - - - - - - - - - > 1X 34 : 1 0 0 0 2 0 0 0 < - - - - - - - - - DATA FOR FONT 3 - - - - - - - - - - > 5X 78 Fig.18 Character font pattern stored in ROM1 and ROM2. 1996 Jan 08 24 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (a) Character designed in character ROM 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (b) North shadowing background mode display on screen MLB402 Fig.19 Combination of two character cells to form new font (in horizontal direction). 1996 Jan 08 25 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 0 1 2 3 4 5 6 7 8 9 10 11 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 0 1 2 If Row 0 of the lower character 3 does not contain the bit 4 pattern of Row 18 of 5 the upper character 6 in North shadowing 7 mode, a gap in the 8 shadow might occur 9 10 11 12 13 14 15 16 17 ,, MLB403 0 1 2 3 4 5 6 7 8 9 10 11 Character pattern stored in character ROM Character pattern displayed on the screen Fig.20 Combination of two character fonts in a vertical direction - with gap. 1996 Jan 08 26 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 0 1 2 3 4 5 6 7 8 9 10 11 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 0 1 2 Row 0 of the lower character 3 should contain the bit 4 pattern of Row 18 of 5 the upper character 6 in North shadowing mode 7 to avoid a "break" in the 8 shadow 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 MLB404 Character pattern stored in the character ROM Character pattern displayed on the screen Fig.21 Combination of two character fonts in a vertical direction - without gap. 1996 Jan 08 27 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12 OSD CONTROL REGISTERS PCE84C886 The functions of the OSD are controlled by Derivative Registers 22, 23, 33, 34, 35, 36 and 37. An overview of the function of each register is given in Table 16. A full description of each register is given in Sections 12.1 to 12.7. Table 16 OSD Control Registers overview REGISTER NAME CON1 CON2 CON3 CON4 REGISTER NUMBER Derivative Register 22 Derivative Register 23 Derivative Register 33 Derivative Register 34 ADDRESS (HEX) 22 23 33 34 FUNCTION This register is used to enable PWM8; the I2C-bus lines; the ADC channels and the VOW0 and VOW1 lines. This register selects the output polarity of the PWM outputs and also enables and selects the VSYNCN interrupt. This register selects the blinking frequency and the active ratio of the blinking frequency for the OSD. This register selects the 4 display modes; the active state of the HSYNCN and VSYNCN inputs and the output polarity of the FB and VOW0 to VOW2 outputs. It also enables/disables the OSD clock. This register selects the vertical starting position of the display row. This register selects the horizontal starting position of the display row. This register selects the background colour in Frame shadowing mode. VPOS HPOS FRC Derivative Register 35 Derivative Register 36 Derivative Register 37 35 36 37 1996 Jan 08 28 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.1 Derivative Register 22 PCE84C886 This register is used to enable PWM8; the I2C-bus lines; the ADC channels and the VOW0 and VOW1 lines. Table 17 Derivative Register 22 7 PWM8E 6 SCLE 5 SDAE 4 ADC2E 3 ADC1E 2 ADC0E 1 VOW1E 0 VOW0E Table 18 Description of Derivative Register 22 bits BIT 7 SYMBOL PWM8E DESCRIPTION Pulse Width Modulated output PWM8 enable bit. When PWM8E = 1; pin 9 is selected as an output for PWM8. When PWM8E = 0; pin 9 is selected as Derivative Port line DP13 and the PWM function is disabled. I2C-bus clock enable bit. When SCLE = 1; pin 39 is selected as the I2C-bus clock line. When SCLE = 0; pin 39 is selected as Derivative Port line DP21 and the I2C-bus function is disabled. I2C-bus data enable bit. When SDAE = 1; pin 40 is selected as the I2C-bus data line. When SDAE = 0; pin 40 is selected as Derivative Port line DP20 and the I2C-bus function is disabled. ADC Channel 2 enable bit. When ADC2E = 1; Channel 2 is enabled. When ADC2E = 0; Channel 2 is disabled. ADC Channel 1 enable bit. When ADC1E = 1; Channel 1 is enabled. When ADC1E = 0; Channel 1 is disabled. ADC Channel 0 enable bit. When ADC0E = 1; Channel 0 is enabled. When ADC0E = 0; Channel 0 is disabled. VOW1E enable bit, When VOW1E = 1; pin 3 is selected as the VOW1 output. When VOW1E = 0; pin 3 is selected as Derivative Port line DP22 and the VOW function is disabled. VOW0E enable bit, When VOW0E = 1; pin 4 is selected as the VOW0 output. When VOW0E = 0; pin 4 is selected as Derivative Port line DP23 and the VOW function is disabled. 6 SCLE 5 SDAE 4 3 2 1 ADC2E ADC1E ADC0E VOW1E 0 VOW0E 1996 Jan 08 29 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.2 Derivative Register 23 PCE84C886 This register selects the output polarity of the PWM outputs and also enables and selects the VSYNCN interrupt. Table 19 Derivative Register 23 7 VINT 6 VIEN 5 - 4 - 3 - 2 P8LVL 1 P7LVL 0 P6LVL Table 20 Description of Derivative Register 23 bits BIT 7 SYMBOL VINT DESCRIPTION VSYNCN/SIO interrupt indication bit. This bit indicates which of the two possible interrupt sources, the Vsync signal (at the VSYNCN pin) or the SIO, generated the interrupt. The interrupt causes the program to jump to the I2C interrupt subroutine at address 05H. If VINT = 1; then the interrupt was generated by Vsync. If VINT = 0; then the I2C-bus generated the interrupt.This bit must be reset after the interrupt has been serviced, otherwise additional unwanted interrupts will be generated. VSYNCN interrupt enable bit. When the SIO interrupt is enabled and VIEN = 1; the Vsync signal (at the VSYNCN pin) will generate an interrupt to the CPU. The VSYNCN interrupt is edge-triggered and can be selected to become active, using the Vp bit in Register 34, on the rising or falling edge of the Vsync signal. In order to generate a VSYNCN interrupt at the start of the vertical back tracing period, the Vp bit must be set correctly; see Section 12.4. The VSYNCN interrupt and the I2C-bus interrupt share the same interrupt vector. These three bits are reserved. 6 VIEN 5 4 3 2 1 0 - - - P8LVL P7LVL P6LVL Polarity select bit for output PWM8. When P8LVL = 0; the PWM8 output is not inverted. When P8VL = 1; the PWM8 output is inverted. Polarity select bit for outputs PWM0 to PWM3. When P7LVL = 0; the PWM outputs are not inverted. When P7LVL = 1; the PWM outputs are inverted. Polarity select bit for outputs PWM4 to PWM7. When P6LVL = 0; the PWM outputs are not inverted. When P6LVL = 1; the PWM outputs are inverted. 1996 Jan 08 30 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.3 Derivative Register 33 PCE84C886 Derivative Register 33 controls the character blinking functions. Table 21 Derivative Register 33 7 - 6 - 5 - 4 - 3 BR1 2 BR0 1 BF1 0 BF0 Table 22 Description of Derivative Register 33 bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - - - BR1 BR0 BF1 BF0 Blinking active ratio select bits. These two bits allow one from a choice of three active blinking ratios to be selected; see Table 23. Blinking frequency select bits. These two bits allow one from a choice of four blinking frequencies to be selected; see Table 24. These 4 bits are reserved. DESCRIPTION Table 23 Selection of Blinking active ratio BR1 0 0 1 1 BR0 0 1 0 1 3 : 1; this is also the default setting. 1:1 1:3 reserved ACTIVE RATIO Table 24 Selection of Blinking frequency BF1 0 BF0 0 f Vsync ------------16 f Vsync ------------32 f Vsync ------------64 f Vsync ------------- ; this is also the default setting. 128 BLINKING FREQUENCY (Hz) 0 1 1 0 1 1 1996 Jan 08 31 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.3.1 THE DISPLAY OF SPACE AND CARRIAGE RETURN CHARACTERS IN THE 4 DISPLAY MODES PCE84C886 * Mode 2: Box shadowing mode. The Space Code is displayed as a transparent pattern with selected background colour. This will also be the background colour of the character following the Space Code. However, when the Space Code is used as an end bit, it will be displayed as a transparent pattern superimposed on the video (see Fig.29). The Carriage Return Code in Mode 2 is also displayed as a transparent pattern superimposed on the video signal. * Mode 3: Frame shadowing mode. The Space Code and the Carriage Return Code are both displayed as transparent patterns with background colour (see Fig.25). Figures 22 to 25 show the display of Space and Carriage Return Characters in the 4 display modes, with the Blinking function ON and OFF. * Mode 0: No background mode. Both the Space Code and the Carriage Return Code are displayed as transparent (no bit) patterns, with the video signal as the background. This is shown in Fig.22. * Mode 1: North shadowing mode. Both codes are displayed in the same manner as for Mode 0. This is shown in Fig.23. , , , ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, SP code Character ON , ,, , ,, ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,, CR code ,, ,, ,, ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, SP code Character OFF , ,, , ,, ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,, CR code MLB397 Fig.22 Blinking in No background (superimpose) mode. ,, ,, ,, ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, SP code Character ON ,, , ,, , ,,,, , ,, ,,, ,, ,, ,, ,,,, ,, ,, ,,, ,, CR code Fig.23 Blinking in North shadowing mode. ,,, , ,, ,, ,, SP code ,,, ,, ,,, ,, , ,,,,,, ,,, ,,, ,,, ,,,,,, ,,, , CR code Character OFF ,,, ,, ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, MLB398 1996 Jan 08 32 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 , , , ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, SP code Character ON , ,, , ,, ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,, CR code ,, ,, ,, ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, SP code SP code Character OFF , ,, , ,, ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,, CR code MLB399 Fig.24 Blinking in Box shadowing mode. SP code CR code CR code Character ON Character OFF MLB401 Fig.25 Blinking in Frame shadowing mode. 1996 Jan 08 33 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.4 Derivative Register 34 PCE84C886 This register selects the 4 display modes; the active state of the signal at the HSYNCN and VSYNCN inputs and the output polarity of the FB and VOW0 to VOW2 outputs. It also enables/disables the OSD clock. Table 25 Derivative Register 34 7 - 6 - 5 S1 4 S0 3 Hp 2 Vp 1 Bp 0 EN Table 26 Description of Derivative Register 34 bits BIT 7 6 5 4 3 SYMBOL - - S1 S0 Hp HSYNCN signal polarity control bit. When Hp = 0, the active level of the signal at the HSYNCN input is LOW; this is also the default state. When Hp = 1, the active level of the signal at the HSYNCN input is HIGH. See Fig.15. VSYNCN signal polarity control bit. When Vp = 0, the active level of the signal at the VSYNCN input is LOW; this is also the default state. When Vp = 1, the active level of the signal at the VSYNCN input is HIGH. See Fig.15. Output polarity control bit for FB, VOW0, VOW1 and VOW2. When Bp = 1; these outputs are active HIGH; this is also the default state. When Bp = 0; these outputs are active LOW. OSD clock enable/disable bit. When EN = 1; the OSD clock is enabled. When EN = 0; the OSD clock is disabled. Display mode select bits on a frame basis; see Table 27. These two bits are reserved. DESCRIPTION 2 Vp 1 Bp 0 EN Table 27 Selection of Display Modes S1 0 0 S0 0 1 DISPLAY MODE Mode 0: No background (superimpose) mode. The OSD characters are superimposed on the monitor video signals. See Fig.26. Mode 1: North shadowing mode. The characters' shadows are generated as if a light source was placed North of the character (see Fig.27). Character shadowing only appears within the cell boundary. Consequently, if Row 18 contains a bit pattern then North shadowing will not be shown on the screen (see Fig.19). The depth of shadow displayed is dependent upon the character size. Characters with sizes of 1H/1V; 1H/2V and 1H/3V have a depth of shadow equivalent to 1 scan line whereas a character of size 1H/4V has a depth of shadow equivalent to 2 scan lines. Examples of characters with North shadowing, for the 4 character sizes, are shown in Fig.28. Mode 2: Box shadowing mode. A background dot matrix of 12 x 18 bits surrounds the character font; where there is no foreground dot a background dot is displayed (see Fig.29). Mode 3: Frame shadowing mode. A background colour fills the whole screen when no bit patterns are being displayed (see Fig.30). 1 of 8 background colours can be selected using Derivative Register 37; the default background colour is blue. 1 0 1 1 1996 Jan 08 34 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth MOS SP code SP code SP code scan line FB R G B "M" : Red + Blue "O" : Blue "S" : Red + Green MLC077 Fig.26 Mode 0: No background (superimpose) mode. 1996 Jan 08 35 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth scan line FB R G B 1st character : Green 2nd character : Blue Character background shadowing : Red MLC078 Fig.27 Mode 1: North shadowing background mode. 1996 Jan 08 36 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 0 1 MLB396 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (a) Character designed in character ROM (b) 1H/2V or 1H/4V character displayed on the screen 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (c) 1H/1V character displayed on the screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (d) 1H/3V character displayed on the screen Fig.28 Example of North shadowing mode. 1996 Jan 08 37 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth ,,, S ,,,, MO ,,, ,,,, SP code SP code SP code (End) scan line FB R G B "M" : Foreground - Red + Blue Background - Green "O" : Foreground - Blue Background - Red "S" : Foreground - Red + Green Background - Blue MLC079 Fig.29 Mode 2: Box shadowing (background) mode. 1996 Jan 08 38 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth MOS SP code SP code SP code scan line FB R G B "M" : Red + Blue "O" : Blue "S" : Red + Green Frame background : Green MLC080 Fig.30 Mode 3: Frame shadowing mode. 1996 Jan 08 39 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.5 Derivative Register 35 PCE84C886 Derivative Register 35 selects the vertical starting position of the display row. Table 28 Derivative Register 35 7 - 6 - 5 V5 4 V4 3 V3 2 V2 1 V1 0 V0 Table 29 Description of Derivative Register 35 bits. BIT 7 6 5 4 3 2 1 0 12.6 SYMBOL - - V5 V4 V3 V2 V1 V0 These 6 bits enable 1 of 64 vertical start positions to be selected for the display row. The vertical starting position is calculated as follows: VP = [ 4 x ( V5 V0 ) ] x horizontal scan lines Where (V5 V0) is the decimal value of the contents of Register 35; (V5 V0) 0. These 2 bits are reserved. DESCRIPTION Derivative Register 36 Derivative Register 36 selects the horizontal starting position of the display row. Table 30 Derivative Register 36 7 - 6 - 5 H5 4 H4 3 H3 2 H2 1 H1 0 H0 Table 31 Description of Derivative Register 36 bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - H5 H4 H3 H2 H1 H0 These 6 bits enable 1 of 64 horizontal start positions to be selected for the display row. The horizontal starting position is calculated as follows: HP = [ 4 x ( H5 H0 ) + 5 ] x OSD clock Where (H5 H0) is the decimal value of the contents of Register 36; (H5 H0) 10. These 2 bits are reserved. DESCRIPTION 1996 Jan 08 40 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 12.7 Derivative Register 37 PCE84C886 Derivative Register 37 selects the background colour when the OSD is in Frame shadowing mode. Table 32 Derivative Register 37 7 - 6 - 5 - 4 - 3 - 2 FRR 1 FRG 0 FRB Table 33 Description of Derivative Register 37 bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - - - - FRR FRG FRB These three bits are used to select the background colour in Frame shadowing mode; see Table 34. The default colour is blue. These 5 bits are reserved. DESCRIPTION Table 34 Selection of Background colour FRR (RED) 0 0 0 0 1 1 1 1 FRG (GREEN) 0 0 1 1 0 0 1 1 FRB (BLUE) 0 1 0 1 0 1 0 1 black blue green cyan red magenta yellow white COLOUR 1996 Jan 08 41 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 13 TO FORMAT THE OSD 13.1 Number of characters per row 13.3 PCE84C886 Character size selection for different display resolutions The number of characters per row is a function of character width. The width of the character displayed is only dependent upon the value held in the 7-bit programmable counter (PLLCN) and is not affected by a change in horizontal resolution (any change in fHsync will be reflected by a linear change in the frequency of the OSD clock). The maximum number of characters per row can be determined by calculating the number of OSD clock pulses that occur during the Hsync active period and dividing the result by the number of horizontal dots in the character matrix (which is 12). If Hsync is assumed to be active for 85% of its cycle period then the maximum number of characters per row (N) can be calculated as follows: 0.85 x f OSD N = ---------------------------12 x f Hsync 13.2 Number of rows per frame To cater for the variable display resolutions (640 x 400, 640 x 480, 800 x 600, 1024 x 768 and 1 280 x 1 024) of auto-sync monitors, the PCE84C886 offers a choice of 4 different character sizes: 1H/1V, 1H/2V, 1H/3V and 1H/4V. This allows the height of displayed characters to be of similar size even when the monitors resolution is changed (see Table 35). Table 35 Recommended character size selection for different display resolutions RESOLUTION 640 x 400 640 x 480 800 x 600 1 024 x 768 1280 x 1024 CHARACTER SIZE 1H/2V 1H/2V 1H/3V 1H/4V 1H/4V ROWS/FRAME 11 13 11 10 14 The number of rows per frame is a function of character height and the spacing between the rows of characters. The height of a character displayed on the screen is determined by the number of visible scan lines per frame and the character size. The number of scan lines is dependent upon the resolution of the monitor; character size is selected by the user (see Section 10.1.2). The PCE84C886 also provides a choice of four inter-line spaces: 0H, 4H, 8H and 12H (see Section 10.1.2). If the inter-line spacing is assumed to be zero then the number of rows per frame (R) can be calculated by dividing the number of visible scan lines (SL) by the character size (CS) and dividing the result by the number of vertical dots in the character matrix (which is 18). This can be expressed mathematically as follows: SL R = -------------------18 x CS Table 35 shows the number of rows per frame for different horizontal resolutions. 1996 Jan 08 42 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 14 8-BIT COUNTER (T3) One application for this counter is in the frequency measurement of the Hsync signal. The block diagram of the 8-bit counter is shown in Fig.31. A Schmitt trigger is used at the input for noise rejection and also to shape the input signal into a square wave. The rising edge of the input increments the ripple counter by `1'. The minimum distance between the rising edges of two successive input pulses is 10 s; the minimum pulse width (HIGH-to-LOW level) of the input is 1 s. T3 may be read using the instruction MOV A, D24 (where D24 is Derivative Register 24). To ensure that a valid read operation has been carried out, the counter needs to be read at least twice. As soon as data is read, the counter is reset to zero. The counter is also reset to zero on overflow or Power-on-reset. The piggy-back device to be used with the PCE84C886 is the PCA84C841B. As this piggy-back device is also used with other microcontrollers in the 84CXXXA family, in order to prevent contention between the T3 pin of the PCE84C886 and the corresponding pin P13 used by the other microcontrollers, when writing to Port 1, P13 must be set to a logic 1 (this port line is not available in the PCE84C886). 15 I2C-BUS INTERFACE PCE84C886 The PCE84C886 has an on-chip I2C-bus interface that can be used in master or slave mode. Full details of the I2C-bus are given in the document "The I2C-bus and how to use it". This document may be ordered using the code 9398 393 40011. The I2C-bus interface lines SDA and SCL share the same pins as Derivative Port lines DP20 and DP21 respectively. Selection of the pin function as either an I2C-bus line or a Derivative Port line is achieved using the SDAE and SCLE bits in Derivative Register 22 (see Section 12.1). Only port Option 2 is available for both of these pins. handbook, full pagewidth T3 CK RESET 8-BIT COUNTER READ ENABLE Q0 to Q7 Data bus Power-on-reset READ D24 MLC075 Fig.31 Block diagram of the 8-bit counter (T3). 1996 Jan 08 43 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 16 OUTPUT PORTS Each I/O port line may be individually configured using one of three mask options. The three I/O mask options are specified below: Option 1 Standard input/output with switched pull-up current source; this is shown in Fig.32. Option 2 Input/output with Open drain output; this is shown in Fig.33. Option 3 Push-pull output; this is shown in Fig.34. The state of each output port after a Power-on-reset can also be selected using the mask options. All port mask options are given in Section 16.1. PCE84C886 WRITE PULSE handbook, full pagewidth OUTL/ORL/ANL/MOV TR2 TR3 DATA BUS D MQ D SQ constant current source 100 A typ. VDD MASTER SLAVE SQ TR1 I/O PORT LINE VSS ORL/ANL/MOV MLA696 IN/MOV Fig.32 Standard I/O with pull-up current source (Option 1). 1996 Jan 08 44 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 handbook, full pagewidth WRITE PULSE OUTL/ORL/ANL DATA BUS D MQ D SQ VDD MASTER SLAVE SQ TR1 I/O PORT LINE VSS ORL/ANL MLA697 IN Fig.33 I/O with open-drain output (Option 2). WRITE handbook, full pagewidth PULSE OUTL / ORL / ANL TR2 VDD constant current source 100 A typ. OUTPUT LINE DATA BUS D MQ D SQ MASTER SLAVE SQ TR1 VSS ORL / ANL MLB998 IN Fig.34 Push-pull output (Option 3). 1996 Jan 08 45 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 16.1 Mask options PCE84C886 Table 36 lists the port mask options for the PCE84C886. Table 37 is intended for customer use when ordering the device. Table 36 Port options OPTION PORT P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P14 DP00 DP01 DP02 DP03 DP04 DP05 DP06 DP07 DP10 DP11 DP12 DP13 DP20 DP21 DP22 DP23 FB VOW2 PIN CONFIGURATION 13 14 15 16 17 18 19 20 7 8 10 12 29 28 27 26 25 24 23 22 38 37 36 9 40 39 3 4 1 2 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 1, 2 or 3 2 2 1, 2 or 3 1, 2 or 3 2 or 3 2 or 3 RESET STATE HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW HIGH HIGH HIGH or LOW HIGH or LOW HIGH or LOW HIGH or LOW PORT P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P14 DP00 DP01 DP02 DP03 DP04 DP05 DP06 DP07 DP10 DP11 DP12 DP13 DP20 DP21 DP22 DP23 FB VOW2 PIN CONFIGURATION 13 14 15 16 17 18 19 20 7 8 10 12 29 28 27 26 25 24 23 22 38 37 36 9 40 39 3 4 1 2 2 2 S S RESET STATE Table 37 Customer selected mask options OPTION 1996 Jan 08 46 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 17 DERIVATIVE REGISTERS PCE84C886 There are 30 Derivative Registers in the PCE84C886. The Derivative Port I/O registers are located at addresses 00 to 05H. When DP0TR, DP1TR and DP2TR are read the data is read directly from the pin. However, when DP0R, DP1R and DP2R are read the data is read from the port latch (see Figs 32 to 34 for the port configuration). Table 38 Register map (see note 1) ADDR (HEX) 00 01 02 03 04 05 10 11 12 13 14 15 16 17 18 19 20 21 22 REG DP0TR DP1TR DP2TR DP0R DP1R DP2R PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8L PWM8H ADCCN PWME CON1 7 DP07 (X) - (X) - (X) DP07 (1) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) 6 DP06 (X) - (X) - (X) DP06 (1) - (X) - (X) PWM06 (0) PWM16 (0) PWM26 (0) PWM36 (0) - (X) - (X) - (X) - (X) 5 DP05 (X) - (X) - (X) DP05 (1) - (X) - (X) PWM05 (0) PWM15 (0) PWM25 (0) PWM35 (0) PWM45 (0) PWM55 (0) PWM65 (0) PWM75 (0) 4 DP04 (X) - (X) - (X) DP04 (1) - (X) - (X) PWM04 (0) PWM14 (0) PWM24 (0) PWM34 (0) PWM44 (0) PWM54 (0) PWM64 (0) PWM74 (0) 3 DP03 (X) DP13 (X) DP23 (X) DP03 (1) DP13 (1) DP23 (1) PWM03 (0) PWM13 (0) PWM23 (0) PWM33 (0) PWM43 (0) PWM53 (0) PWM63 (0) PWM73 (0) 2 DP02 (X) DP12 (X) DP22 (X) DP02 (1) DP12 (1) DP22 (1) PWM02 (0) PWM12 (0) PWM22 (0) PWM32 (0) PWM42 (0) PWM52 (0) PWM62 (0) PWM72 (0) 1 DP01 (X) DP11 (X) DP21 (X) DP01 (1) DP11 (1) DP21 (1) PWM01 (0) PWM11 (0) PWM21 (0) PWM31 (0) PWM41 (0) PWM51 (0) PWM61 (0) PWM71 (0) 0 DP00 (X) DP10 (X) DP20 (X) DP00 (1) DP10 (1) DP20 (1) PWM00 (0) PWM10 (0) PWM20 (0) PWM30 (0) PWM40 (0) PWM50 (0) PWM60 (0) PWM70 (0) R/W R R R RW RW RW RW RW RW RW RW RW RW RW PWM86L PWM85L PWM84L PWM83L PWM82L PWM81L PWM80L RW (0) (0) (0) (0) (0) (0) (0) PWM86H PWM85H PWM84H PWM83H PWM82H PWM81H PWM80H RW (0) (0) (0) (0) (0) (0) (0) ADCS1 (0) ADCS0 (0) PWM5E (0) SDAE (0) DAC3 (0) PWM4E (0) ADCE2 (0) DAC2 (0) PWM3E (0) ADCE1 (0) DAC1 (0) PWM2E (0) ADCE0 (0) DAC0 (0) PWM1E (0) VOW1E (0) COMP(2) (0) PWM0E (0) VOW0E (0) RW RW RW PWM7E PWM6E (0) (0) PWM8E SCLE (0) (0) 1996 Jan 08 47 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications ADDR (HEX) 23 24 25 30 31 32 33 34 35 36 37 Notes REG CON2 T3CON PLLCN DCRAR DCRTR DCRCR CON3 CON4 VPOS HPOS FRC 7 VINT (0) T3B7 (0) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) 6 VIEN (0) T3B6 (0) PLL6 (0) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) - (X) T3B5 (0) PLL5 (0) DCRA5 (0) - (X) DCRC5 (1) - (X) S1 (0) V5 (1) H5 (0) - (X) 5 - (X) T3B4 (0) PLL4 (0) DCRA4 (0) - (X) DCRC4 (1) - (X) S0 (0) V4 (1) H4 (0) - (X) 4 - (X) T3B3 (0) PLL3 (0) DCRA3 (0) DCRT3 (1) DCRC3 (1) BR1 (0) Hp (0) V3 (1) H3 (0) - (X) 3 2 P8LVL (0) T3B2 (0) PLL2 (0) DCRA2 (0) DCRT2 (1) DCRC2 (1) BR0 (0) Vp (0) V2 (1) H2 (0) FRR (0) 1 P7LVL (0) T3B1 (0) PLL1 (0) DCRA1 (0) DCRT1 (1) DCRC1 (1) BF1 (1) Bp (1) V1 (1) H1 (0) FRG (0) PCE84C886 0 P6LVL (0) T3B0 (0) PLL0 (0) DCRA0 (0) DCRT0 (1) DCRC0 (1) BF0 (1) EN (0) V0 (1) H0 (0) FRB (1) R/W RW R RW RW W W RW RW W W W 1. Values within parenthesis show the bit state after a reset operation. `X' denotes an undefined state. 2. This bit is Read only. 18 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 34). SYMBOL VDD VI IOH IOL Ptot Tamb Tstg supply voltage input voltage on any pin with respect to ground (VSS) maximum source current for all port lines maximum sink current for all port lines total power dissipation operating ambient temperature storage temperature PARAMETER MIN. -0.3 -0.3 - - - -25 -55 MAX. +8.0 VDD + 0.3 -10.0 30.0 1 +85 +125 V V mA mA W C C UNIT 1996 Jan 08 48 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications PCE84C886 19 DC CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = -25 to +85 C; all voltages with respect to VSS; unless otherwise specified. SYMBOL Supply VDD IDD operating supply voltage operating supply current fOSD = fxtal = 10 MHz fOSD = fxtal = 6 MHz fOSD = Stop; fxtal = 10 MHz fOSD = Stop; fxtal = 6 MHz VPOR VIL VIH ILI VOL IOH1 IOH2 IOL IOH1 IOH2 IOL IOH1 IOH2 IOL IOH1 IOH2 IOL IOH1 IOH2 Power-on-reset voltage level Ports P0, P1, DP0, DP1 and DP2 inputs LOW level input voltage HIGH level input voltage input leakage current VSS < VI < VDD VDD = 5 V; IOL = 10 mA VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS DP00/PWM0 to DP07/PWM7 as derivative ports LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS DP00/PWM0 to DP07/PWM7 as PWM outputs LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS P10 to P14, DP20 and DP21 outputs LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS DP20/SDA and DP21/SCL outputs LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS 3.0 -40 - - -100 -140 -7.0 - - -400 - mA A A mA 5.0 -40 - 12.0 -100 -140 -7.0 - - -400 - mA A A mA 0.7 -40 - 1.5 -100 -140 -1.5 - - -400 - mA A A mA 5.0 -40 - 12.0 -100 -140 -7.0 - - -400 - mA A A mA 0 - - -40 - - - - -100 -140 -7.0 0.3VDD V VDD 10 V A 0.7VDD - 4.5 - - - - 0.7 5.0 5 3.5 3 1.5 1.3 5.5 10 7 6 4 1.9 V mA mA mA mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Port P0 outputs LOW level output voltage HIGH level pull-up output source current 1.2 - -400 - V A A mA HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -3.0 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -3.0 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -0.7 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -3.0 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V - 1996 Jan 08 49 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications SYMBOL PARAMETER CONDITIONS MIN. PCE84C886 TYP. MAX. - - -400 - - - -400 - - - -400 - - - -400 - - - -400 - UNIT VOW1/DP22; VOW0/DP23 and DP13/PWM8 as derivative output ports IOL IOH1 IOH2 IOL IOH1 IOH2 IOL IOH1 IOH2 IOL IOH1 IOH2 IOL IOH1 IOH2 VIL VIH ILI LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS VOW1/DP22 and VOW0/DP23 as VOW outputs LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS DP13/PWM8 as PWM8 output LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS Outputs FB and VOW2 LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS DP10/ADC0 to DP12/ADC2 as derivative output ports LOW level output sink current HIGH level pull-up output source current VDD = 5 V; VOL = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS TEST/EMU; RESET; INTN/T0; T1; HSYNCN; VSYNCN and T3 LOW level input voltage HIGH level input voltage input leakage current VSS < VI < VDD 0 -1.0 - - 0.3VDD V VDD +1.0 V A 0.7VDD - 5.0 -40 - 12.0 -100 -140 -7.0 mA A A mA 1.4 -40 - 3.0 -100 -140 -3.0 mA A A mA 1.4 -40 - 3.0 -100 -140 -3.0 mA A A mA 1.4 -40 - 3.0 -100 -140 -3.0 mA A A mA 5.0 -40 - 12.0 -100 -140 -7.0 mA A A mA HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -3.0 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -1.4 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -1.4 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -1.4 HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -3.0 1996 Jan 08 50 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 20 AC CHARACTERISTICS SYMBOL fxtal PARAMETER Crystal oscillator frequency Option 1: gm = 0.4 mS Option 2: gm = 1.2 mS fPXE fOSD fHsync fVsync COSD Cxtal1 Cxtal2 tT3 PXE resonator frequency Option 2: gm = 1.2 mS OSD clock frequency Hsync frequency Vsync frequency external capacitance at pin C external capacitance at XTAL1 (IN) pin (PXE resonator) external capacitance at XTAL2 (OUT) pin (PXE resonator) minimum pulse width period at T3 input rising or falling edge of T3 pulse < 30 ns duty cycle = 10 : 90 duty cycle = 10 : 90 VDD = 5 V 1 4.0 30 50 - - - 1 - - - - 0.33 30 30 - CONDITIONS VDD = 5 V 1 4 - - MIN. TYP. PCE84C886 MAX. 6 10 6 14 64 120 - 100 100 - UNIT MHz MHz MHz MHz kHz Hz F pF pF s Analog-to-Digital (software) Converter VAI VAE TAFC comparator analog input voltages ADC0; ADC1 and ADC2 conversion error range conversion time (from any change in ADC input i.e. channel number; voltage level or enable/disable) VSS - - - - - VDD 1 2 7 V LSB s 1996 Jan 08 51 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 21 DEVELOPMENT SUPPORT PCE84C886 Table 39 details the hardware items available for development support and Table 40 lists the development support documentation. Table 39 Hardware ITEM LCDS Development System Mother board - LCDS84 Daughter board - LCD84C846 Piggy-back version PCA84C841B Table 40 Documentation DOCUMENT NAME OSD + BCM monitor application board (BCM9211) and software (Version 1.0) OSD + BCM Software Version 1.1 and Monitor Application Board (BCM9211) PCE84C886 OSD microcontroller optimization techniques REPORT NUMBER Taiwan/AN9302 Taiwan/AN9308 Taiwan/AN9311 - 9350 419 50112 OM1025 OM4833 9339 931 50112 9350 426 00112 TYPE ORDER NUMBER 1996 Jan 08 52 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 22 PACKAGE OUTLINE SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) PCE84C886 SOT270-1 seating plane D ME A2 A L A1 c Z e b1 wM (e 1) MH b 42 22 pin 1 index E 1 21 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 90-02-13 95-02-04 1996 Jan 08 53 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 23 SOLDERING 23.1 Introduction PCE84C886 There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 23.2 Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 23.3 Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 1996 Jan 08 54 Philips Semiconductors Preliminary specification Microcontroller for monitor OSD and auto-sync applications 24 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values PCE84C886 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 25 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 26 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jan 08 55 Philips Semiconductors - a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040)23 53 60, Fax. (040)23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 453061/1100/01/pp56 Document order number: Date of release: 1996 Jan 08 9397 750 00551 |
Price & Availability of PCE84C886
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |